(1) Field of the Invention
The present invention relates to the fabrication of a dynamic random access memory (DRAMs) device, and more particularly, a fabrication technique for making microminiaturized storage capacitor used for charge storage.
(2) Description of the Prior Art
Very large scale integration (VLSI) technologies have greatly increased the circuit density on the chip, and have significantly improved the circuit performance and reduced the cost of todays electronic products. Further improvement in the performance to cost ratio depends strongly on continued down scaling of these devices on a VLSI chip. One type of VLSI chip, the dynamic random access memory (DRAMs), is used extensively in the electronic industry and particularly in the computer industry for electrical data storage. These DRAM chips consist of an array of individual cells which store a unit of data (bit) and contain one charge passing transistor, usually a metal-oxide-semiconductor field effect transistor (MOSFET) and a single storage capacitor. In the next 5 to 10 years the number of these cells are expected to reach 256 megabits per chip. To achieve these advances in data storage and maintain a reasonable chip size, the individual cells, on the chip, must be significantly reduced in size.
As these individual memory cells decrease in size, so must the MOSFET charge passing transistor and the storage capacitor decrease in size. However, the reduction in the storage capacitor size makes it difficult to store sufficient charge on the capacitor to maintain an acceptable signal-to-noise level. These smaller storage capacitor also, require shorter refresh cycle times to retain the necessary charge level.
To avoid these problems, others have proposed forming stacked capacitor structures which rely on using self-aligning technique, See, for example, A. Chiba U.S. Pat. No,. 5,102,820. The object of many of these technique is to have the capacitor electrode extend upward and to fold back upon itself, so as to increase the capacitor electrode area without increasing the cell area. These vertical structures, in many cases, rely on forming side walls using etch back techniques to interconnect the various layers. Although these technique are important in semiconductor technologies, it would be preferable to form such vertical structure out of a single continuous layer.